Control system with multiprocessor architecture for an internal combustion powertrain

ABSTRACT

A control system with multiprocessor architecture for an internal combustion powertrain is disclosed. The control system has a computing unit capable of executing both basic control functions of the powertrain and ancillary control functions not directly related to the control of the powertrain. The computing unit comprises a main processor, which is dedicated to executing basic functions for controlling the powertrain, at least one auxiliary processor, which is dedicated to executing ancillary control functions, a number of memories, a series of peripheral devices, at least one peripheral bus connection, to which the peripheral devices are connected, and an intelligent main bus connection of the cross-bar bus type to allow the processors to communicate with the memories and with the peripheral bus connection.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to Italian PatentApplication Serial No. BO2003A 000256 filed Apr. 30, 2003, the contentsof which are incorporated herein by reference.

BACKGROUND OF INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a control system withmultiprocessor architecture for an internal combustion powertrain.

[0004] 2. Description of Related Art

[0005] Known powertrains comprise a control system that is capable ofsupervising the operation of the entire powertrain and comprises asingle-processor computing unit having just one processor. In the greatmajority of cases, a powertrain manufacturer purchases the controlsystem from an external supplier and requests said supplier to ensurethat it is possible to implement control functions in the controlsystem, which functions are intended for electronic devices produced bythe powertrain manufacturer.

[0006] Typically, the producer of the control system tends to oversizethe computing capacity and interconnectivity capacity of the computingunit in order to allow the engineers of the powertrain manufacturer touse the computing unit to implement control functions which they havedeveloped themselves. However, the above-described solution ofoversizing the computing capacity of a single-processor computing unitoften proves inadequate in that execution of the control functionsdeveloped by the engineers of the powertrain manufacturer may interferenegatively with the execution of the powertrain control developed by theproducer of the control system. Moreover, increasing the computingcapacity of a single-processor computing unit can be achieved bymodifying the internal architecture of the processor or by increasingthe operating frequency of the processor itself; however, modifying theinternal architecture of the processor is extremely costly, whileincreasing the operating frequency of the processor can complicate dataexchange by means of existing buses that are designed to operate at aspecific operating frequency.

[0007] U.S. Pat. No. 5,367,665 A1 (issued Nov. 22, 1994) discloses amulti-processor system for a motor vehicle and having at least twoprocessors; the system carries out a first sequence of steps when poweris switched on and, for a restart during operation, executes a secondsequence of steps (the system distinguishes between power on and arestart and selects, the corresponding step sequence). In addition, acheck is provided as to whether the number of resets of a processor hasexceeded a pregiven threshold; in this case, a processor is transferredinto the standby state for the operating cycle, which is then running.

[0008] U.S. Pat. No. 5,454,095 A1 (issued Sep. 26, 1995) discloses amulti-processor system, which has at least two processors jointlyaccessing the same memory and is useful for controlling processes ofmotor vehicles. The system memory is divided into at least two sectors,so as a first processor accesses one memory sector only in the read modeand a second processor accesses it only in the write mode; the secondprocessor accesses the other memory sector only in the read mode and thefirst processor accesses it only in the write mode. The processors aresynchronized in such a way that the processors access the memory in thesame way at the same time.

SUMMARY OF INVENTION

[0009] An object of the present invention is to provide a control systemwith multiprocessor architecture for an internal combustion powertrain,which does not have the above-described disadvantages and, inparticular, is easily and economically implemented.

[0010] The present invention provides a control system withmultiprocessor architecture for an internal combustion powertrain asrecited in the attached claims.

BRIEF DESCRIPTION OF DRAWINGS

[0011] The present invention will now be described with reference to theattached drawings, which illustrate a non-limiting embodiment of theinvention, in which: FIG. 1 is a schematic diagram of an internalcombustion powertrain equipped with the control system withmultiprocessor architecture that is the subject matter of the presentinvention.

[0012]FIG. 2 is a block diagram of the internal architecture of acomputing unit of the control system of FIG. 1.

DETAILED DESCRIPTION

[0013] In FIG. 1, 1 denotes the overall internal combustion powertrainfor a road vehicle (not shown); the powertrain 1 comprises an engine 2equipped with four cylinders 3 (only one of which is shown in FIG. 1),each of which is connected to an intake manifold 4 via a respectiveintake duct 5 controlled by at least one respective intake valve 6 andto an exhaust manifold 7 via a respective exhaust duct 8 controlled byat least one respective exhaust valve 9. The intake manifold 4 receivesfresh air (i.e. air originating from the outside environment) via athrottle valve 10 that is adjustable between a closed position and amaximally open position; from the exhaust manifold 7 there leaves anexhaust device 11 equipped with one or more catalytic converters (notshown in detail) to discharge into the atmosphere the gases produced bycombustion in the cylinders 3.

[0014] Four injectors 12 (one for each cylinder 3) are coupled to therespective intake ducts 5 in order to inject petrol cyclically into saidintake ducts 5; moreover, four spark plugs 13 (one for each cylinder 3)are coupled to the respective cylinders 3 in order cyclically to bringabout ignition of the mixture present inside said cylinders 3.

[0015] Each cylinder 3 is coupled to a respective piston 14, which iscapable of running linearly along the cylinder 3 and is mechanicallyconnected to a powertrain crankshaft 15 by means of an associatedconnecting rod 16; in turn, the powertrain crankshaft 15 is mechanicallyconnected to a gearbox 17 by means of an interposed clutch 18 in orderto transmit drive torque to the drive wheels of the motor vehicle (notshown).

[0016] A control system 19 is associated with the powertrain 1, saidsystem being capable of supervising the operation of the entirepowertrain 1, i.e. the operation of the engine 2, clutch 18 and gearbox17. The control system 19 comprises a computing unit 20 capable ofexecuting both basic control functions of the powertrain 1 and ancillarycontrol functions not directly related to the control of the powertrain1. The basic control functions of the powertrain 1 are the controlfunctions related to the production and transmission of drive torque,such as calculating and actuating the injection time, calculating andactuating the ignition advance, monitoring the composition of theexhaust gases, actuating the clutch 18 and the gearbox 17. The ancillarycontrol functions not directly related to the control of the powertrain1 are control functions that are not implemented by the manufacturer ofthe control system 19 at the time of manufacture of the control system19, but that may or may not be implemented by the manufacturer of thepowertrain 1 after the manufacture of the control system 19. As shown inFIG. 2, the computing unit 20 comprises a main processor 21 intended toexecute basic control functions of the powertrain 1, at least oneauxiliary processor 22 intended to execute ancillary control functions,a number of RAM type memories 23, a number of ROM type memories 24, aseries of peripheral devices 25 of known type, a pair of peripheral busconnections 26 and 27 to which the peripheral devices 25 are connectedin a known manner, and a main bus connection 28 through a cross-barswitch of the cross-bar bus type in order to allow the processors 21 and22 to communicate with the memories 23 and 24 and with the peripheralbus connections 26 and 27 while avoiding the occurrence of conflictingcommunication operations by means of suitable access arbitration.According to an alternative embodiment, not shown, the computing unit 20comprises further auxiliary processors 22.

[0017] The computing unit 20 preferably comprises a single integratedcircuit 29 that accommodates the processors 21 and 22, the memories 23and 24, the main bus connection 28 and the peripheral bus connections 26and 27, so providing an architecture generally known as “system onchip”.

[0018] In general, the peripheral bus connection 26 is intended forconnecting slow peripheral devices 25, such as “CAN”, “SPI” and “TIMERUNIT” devices, while the peripheral bus connection 27 is intended forconnecting high speed peripheral devices 25, such as “A/D CONVERTER” and“DMA” devices.

[0019] It is important to emphasize that the auxiliary processor 22 canexecute inter-processor interrupt operations in order to wait for themain processor 21 to complete a particular computing algorithm; however,the opposite is not usually true, i.e. the main processor 21 shouldnever have to wait for the auxiliary processor 22 to complete aparticular computing algorithm. To state matters more clearly, it istheoretically possible for the main processor 21 to wait for theauxiliary processor 22 to complete a particular computing algorithm byusing an inter-processor interrupt operation, but this option should notbe used in order to ensure that the execution of basic control functionsof the powertrain 1 cannot in any way be slowed down by ancillarycontrol functions.

[0020] In order to ensure optimum operation of the computing unit 20,the memories 23 and 24 may at least in part be protected: a firstportion of the memories 23 and 24 is reserved for the main processor 21,and a second portion of the memories 23 and 24, different from the firstportion, is reserved for the auxiliary processor 22.

[0021] From the above explanation, it is clear that the main processor21 operates entirely autonomously with regard to the auxiliary processor22, while the auxiliary processor 22 can operate either entirelyautonomously with regard to the main processor 21 or dependently on themain processor 21. In this manner, the control system 19 is able torender the execution of the basic control functions of the powertrain 1and of the ancillary control functions completely independent andparallel.

[0022] Finally, it is important to emphasise that at the time ofmanufacture of the control system 19, it is only the basic controlfunctions of the powertrain 1 that are implemented in the computing unit20; the ancillary control functions may or may not be implemented in thecomputing unit 20 at another time by the manufacturer of the powertrain1 or of the road vehicle (not illustrated) that accommodates thepowertrain 1.

[0023] As a result of the many advantages offered by the above-describedcontrol system 19 for the powertrain 1, with multiprocessorarchitecture, said control system 19 can profitably be used forcontrolling any kind of internal combustion powertrain.

[0024] In particular, the control system 19 has great flexibility in thedesign of the control architecture, makes it readily feasible tointegrate control functions implemented after the manufacture of thecontrol system 19, and does not exhibit unwanted and/or uncontrolledinterference between the basic control of the powertrain 1 and thecontrol functions implemented after the production of the control system19.

1. A control system (19) with multiprocessor architecture for aninternal combustion powertrain (1); the control system (19) comprising acomputing unit (20) capable of executing both basic control functions ofthe powertrain (1) and ancillary control functions not directly relatedto the control of the powertrain (1); the control system (19) beingcharacterized in that the computing unit (20) comprises a main processor(21) dedicated to executing basic functions for controlling thepowertrain (1), at least one auxiliary processor (22) dedicated toexecuting ancillary control functions, a number of memories (23, 24), aseries of peripheral devices (25), at least one peripheral busconnection (26, 27), to which the peripheral devices (25) are connected,and a main bus connection (28) through a cross-bar switch of thecross-bar bus type to allow the processors (21, 22) to communicate withthe memories (23, 24) and with the peripheral bus connection (26, 27)while avoiding the occurrence of conflicting communication operations.2. The control system (19) of claim 1, in which the computing unit (20)comprises a first peripheral bus connection (26), which is intended forconnecting slow peripheral devices (25), and a second peripheral busconnection (27), which is intended for connecting high speed peripheraldevices (25).
 3. The control system (19) of claim 1, in which thememories (23, 24) comprise either RAM type memories (23) or ROM typememories (24) and can at least in part be protected, a first portion ofthe memories (23, 24) being reserved for the main processor (21), and asecond portion of the memories (23, 24), different from the firstportion, being reserved for the auxiliary processor (22).
 4. The controlsystem (19) of claim 1, in which the computing unit (20) comprises asingle integrated circuit (29) that accommodates the processors (21,22), the memories (23, 24), the peripheral bus connections (26, 27) andthe main bus connection (28).
 5. The control system (19) of claim 1, inwhich the auxiliary processor (22) can execute inter-processor interruptoperations in order to wait for the main processor (21) to complete aparticular computing algorithm.
 6. The control system (19) of claim 5,in which the main processor (21) does not execute inter-processorinterrupt operations in order to wait for the auxiliary processor (22)to complete a particular computing algorithm.
 7. A control system (19)with multiprocessor architecture for an internal combustion powertrain(1); the control system (19) comprising a computing unit (20) capable ofexecuting both basic control functions of the powertrain (1) andancillary control functions not directly related to the control of thepowertrain (1); the control system (19) being characterized in that thecomputing unit (20) comprises a main processor (21) dedicated toexecuting basic functions for controlling the powertrain (1), at leastone auxiliary processor (22) dedicated to executing ancillary controlfunctions, a number of memories (23, 24), a series of peripheral devices(25), at least one peripheral bus connection (26, 27), to which theperipheral devices (25) are connected, and a main bus connection (28)through a cross-bar switch of the cross-bar bus type to allow theprocessors (21, 22) to communicate with the memories (23, 24) and withthe peripheral bus connection (26, 27) while avoiding the occurrence ofconflicting communication operations; the auxiliary processor (22) canexecute inter-processor interrupt operations in order to wait for themain processor (21) to complete a particular computing algorithm and themain processor (21) does not execute inter-processor interruptoperations in order to wait for the auxiliary processor (22) to completea particular computing algorithm.